1. Field of the Invention
This invention relates generally to an enhanced method of testing semiconductor devices. More specifically, this invention relates to an enhanced method of testing regions of semiconductor devices in order of probability that a defect will occur in the regions. Even more specifically, this invention relates to an enhanced method of testing semiconductor devices that contain nonvolatile memory elements. Furthermore, this invention relates to an enhanced method of testing semiconductor devices that contain nonvolatile memory elements that avoids the necessity for the multiple programming and erasing of the nonvolatile memory elements.
2. Discussion of the Related Art
There are many semiconductor devices that utilize nonvolatile devices such as EPROMs (Erasable Programmable Read Only Memories) and EEPROMs (Electrically Erasable Read Only Memories) that retain their contents upon termination of power. One such device is a programmable logic device (PLD), which is a programmable integrated circuit that allows the end user or customer of the circuit to customize the logic functions the circuit is to perform. The term PLD is a generic term and includes other "array" programmable logic devices, such as PLAs (Programmable Logic Arrays), PALs (Programmable Array Logic) devices, and GALs (Generic Array Logic) devices. These programmable logic devices can be programmed to perform logic functions previously performed by small, medium and large-scale integrated circuits.
When a typical programmable logic device is delivered to a customer, it is not yet capable of performing any specific function. The customer, using software typically supplied by the manufacturer of the programmable logic devices, programs the PLD to perform the specific function or functions required by the customer's application. The PLD is then capable of functioning in a larger system designed by the customer in the same way dedicated logic chips would perform if used in the system.
The manufacture and sale of PLDs has become a substantial and important sector of the semiconductor industry. The success of these devices has caused a dramatic increase in the demand for programmable devices that can be programmed to accommodate larger and more complex customer programmable patterns. Because customers expect and demand devices that are 100% tested, the importance of efficient test methodologies has become paramount. It is well known in the semiconductor industry that as semiconductor products mature, their selling prices fall dramatically. This fall in selling prices makes it even more imperative that manufacturing costs and related testing costs be reduced in order to maintain a reasonable margin of profitability for the devices as they mature.
A typical PLD includes a number of product term arrays (PTAs), which are arrays of logic cells that can be individually programmed and arbitrarily interconnected to each other by the customer. The interconnections provide further internal input signals as well as output signals that permit the performance of highly complex combinational and sequential logic functions. The customer is provided with a "customer" program that is implemented in the PLD by allowing the customer to set the states of programmable elements in the PTAs. The programmable elements in the PTAs are memory cells that may be volatile memory cells such as SRAMs that lose their programmed state upon termination of power to the system. The use of volatile memory cells requires the volatile memory cells to be reprogrammed each time power is applied to the circuit. Alternatively, the memory cells may be nonvolatile memory cells, such as EPROMs and EEPROMs, which retain their content upon termination of power thus obviating the requirement to reprogram the memory cells each time power is terminated and reapplied to the circuit.
Programmable logic devices also include multipurpose logic blocks typically called macrocells. These multipurpose logic blocks perform various functions of synchronous and/or asynchronous functions as configured by the customer using the software provided by the manufacturer to program memory cells that control the configuration of the macrocells.
In order to provide the customer with the maximum flexibility in the programming of the PLD, an interconnection harness is provided that can be programmed to provide a path from any input pad on the PAD to any PTA and virtually to any other point within the PLD.
As discussed above, as PLDs have migrated towards higher logical capacity, the testing of the PTAs, the macrocells and the interconnection harness has surfaced to be a non-trivial problem. This problem affects both the costs of the development of high quality test vectors and the cost of testing each PLD. A major portion of testing cost is a direct function of test time.
Presently, in order to fully test the interconnection and logic capacity of a PLD that contains nonvolatile memory elements, many program/erase cycles are required, which substantially increases the testing time for each added cycle. As the programmable logic devices continue to increase in size and complexity it is becoming more difficult and time consuming to guarantee that all of the interconnection circuitry implemented in the PLD has the capability of functioning correctly as programmed by the customer. For example, one implementation of Interconnection circuitry is to use N to 1 multiplexers. Since it is necessary to localize any defects that are detected, both as a quality issue for the test vectors and to assess the quality of fabricated silicon, each input to each multiplexer must be tested separately. Since each input to each of these multiplexers is controlled by a separately programmed nonvolatile memory element a theoretical minimum number of program/erase cycle can be determined by finding the multiplexer with the largest number of inputs. This means that N becomes the minimum number of program/erase cycles. It should be appreciated that more than this theoretical minimum number of program/erase cycles may be required because many other factors, such as additional architectural complexities may add required program/erase cycles.
In order to test the increasingly complex PLDs economically, it is mandatory that the high number of program/erase cycles be controlled or reduced. Of paramount importance is the implementation of a testing methodology that has the capability to identify defective die, as soon as possible, and then to cease testing the identified defective die since test costs are significant. The test costs become even more significant as the selling price of the device decreases in the marketplace. The continued expenditure of testing resources on defective die increases the test cost of good die, since the continued cost of testing defective dice is amortized over the remaining good devices. Currently the testing methodology for PLDs is a "brute force" methodology in which test vectors are generated for each and every interconnect combination in the device without considering in which area of the device it is more likely for manufacturing defects to occur.
Therefore, what is needed is a testing methodology for testing programmable logic devices that can quickly and economically identify defective die as soon as possible in the testing cycle and then to cease testing the defective die. In addition, what is needed is a testing methodology for testing programmable logic devices that avoids the necessity for the program/erase cycle for each test.